1. Technical Field
The present invention relates generally to a semiconductor circuit, and more particularly, to a synchronization circuit.
2. Related Art
A semiconductor circuit may include a synchronization circuit for delay locking or duty cycle compensation, such as a DLL (delay locked loop) or a DCC (duty cycle corrector).
The delay locked loop may be used to change the phase of a clock signal, usually to improve, for example, the clock rise-to-data output valid timing characteristics of integrated circuits such as DRAM devices.
The duty cycle corrector may be used to compensate for a skew in a duty cycle of a clock signal.
In order to accommodate the trend of a semiconductor integrated circuit toward high speed operation, it is preferred that a delay locking operation and a duty cycle correcting operation be performed as quick and precise as possible.